TIA Playfield

The first part of understanding the playfield section of the TIA is to understand the playfield cell. The cell is composed of three sections, a latch section (on the left) which works just like the L block, and two delay sections (on the right) which work as shift registers. Data enters the cell on line I and is latched by signals L1 and L2. Data enters the shift register on SI1(SI2) and is clocked through the register by C1 and C2 and goes out through SO1(SO2). Whenever the output of both shift registers is low, T2 and T4 will be disabled and the output line O will enter a floating state. When the output of either shift register goes high, T2 or T4 will be enabled this connecting the output to either T1 or T3. If the latch is storing a low T1 and T3 will be disabled and the output will still remain in a floating state. On the other hand if the latch is storing a high, T1 and T3 will be enabled and the output line will be pulled low.

Looking at page one of the schematics you can see the Playfield Registers in the lower right. The registers are made up of 20 playfield cells, arranged into two blocks of 8 and one block of 4. The input lines are tied to the data bus and this data is latched into the registers by the address strobes (PF0, PF1, and PF2). The shift registers are cascaded together output to input two form two 20 bit shift registers. The shift registers are clocked by H1 and H2 which are the first two bits of the horiztonal counter.


This circuit control the playfield registers. At the start of each scanline RHB (Reset Horizontal Blank) goes high, gets inverted by the OR gate and then inverted back and become an input to the first shift register. At the center of the screen CNT (center) goes high. If REF (reflect) is high then the AND gate will go high thus passing a high to the input of the first ship register. If REF is low the output the left OR gate will go high this passing a high into the second shift register.

So to put this altogether. The playfield cell latches are loaded from the address bus by the address decodes. When the scanline starts a high is shifted into the first shift register. As the high moves into each cell, the latch output is enabled. If the latch is high the output is pulled low, thus output a low from the cell. If the latch is low the output is left to float and the pull up resistor at the bottom of each register will pull the line high, thus making the output of the register go high. At the center of the playfield a high will be clocked into either the first or second shift register based on the state of the reflect bit. If the first shift register gets the high the second part of the playfield will be clocked out just like the first. If the second shift register gets the high the second part of the playfield will be clocked out in reverse.

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Dan Boris - danlb_2000@yahoo.com